The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a storage node contact in a semiconductor device.
As semiconductor devices become highly integrated, a contact margin between a storage node contact plug and a storage node have decreased, generating limitations such as misalignment. Thus, a storage node contact pad having a large line width is formed over the storage node contact plug to maintain the contact margin between the storage node contact plug and the storage node.
FIGS. 1A to 1E illustrate cross-sectional views of a typical method for fabricating a storage node contact in a semiconductor device. Reference denotation (A) represents a sectional view of a cell region taken along a bit line direction, and reference denotation (B) represents a sectional view of the cell region taken along a word line direction.
Referring to FIG. 1A, a plurality of gate lines 12 are formed over a substrate 11. Sidewall spacers 13 are formed on sidewalls of the gate lines 12. A first insulation layer is formed over the substrate structure. A landing plug contact process is then performed to form landing plugs 15 between adjacent gate lines 12 over the substrate 11. Reference numeral 14 refers to a first insulation pattern 14.
A second insulation layer 16 is formed over the resultant structure. Bit lines BL are formed over certain regions of the second insulation layer 16. The bit lines BL each include a stack structure configured with a bit line tungsten layer 17 and a bit line hard mask 18. Bit line spacers 19 are formed on sidewalls of the bit lines BL. A third insulation layer 20 is formed over the resultant structure. A hard mask layer is formed over the third insulation layer 20. The hard mask layer is etched using a photoresist pattern 22 to form a hard mask pattern 21.
Referring to FIG. 1B, the photoresist pattern 22 is removed. The third insulation layer 20 and the second insulation layer 16 are etched using the hard mask pattern 21 as an etch barrier to form first contact holes 23 exposing the landing plugs 15. The exposed portions of the landing plugs 15 will be coupled to subsequent storage nodes. Reference numerals 16A and 20A refer to a second insulation pattern 16A and a third insulation pattern 20A, respectively.
Referring to FIG. 1C, spacers 24 are formed in the first contact holes 23 (FIG. 1B). A conductive material is filled in the first contact holes 23. An etch-back or chemical mechanical polish (CMP) process is performed to form storage node contact plugs 25 in the first contact holes 23. The hard mask pattern 21 is removed during the etch-back or CMP process.
Referring to FIG. 1D, a fourth insulation layer 26 is formed over the resultant structure. A mask pattern 27 is formed over certain regions of the fourth insulation layer 26. The mask pattern 27 is formed to form subsequent contact pads having a larger line width than the storage node contact plugs 25.
Referring to FIG. 1E, the fourth insulation layer 26 is etched using the mask pattern 27 (FIG. 1D) as an etch barrier to form second contact holes (reference numeral omitted) exposing the storage node contact plugs 25. Reference numeral 26A refers to a fourth insulation pattern 26A. A conductive material is filled in the second contact holes to form storage node contact pads 28. Subsequent storage nodes will be coupled to the storage node contact pads 28.
In the aforementioned typical method, the storage node contact plugs 25 and the storage node contact pads 28 are formed to improve a process margin when forming subsequent storage node contacts. However, the mask and etch processes for forming the storage node contact plugs 25 and the mask and etch processes for forming the storage node contact pads 28 are performed separately. Thus, two sets of mask patterns and etch processes are often required. The increased number of processes may generate limitations such as increased cost of device fabrication process and deteriorated yield.